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Important Things For Power management
Power management chips and BIOS chips, where 3.3VPCU, VC CRT C where
normal electricity supply, will enter the working state. One-chip power
management system can be understood as moments in the work of the monitoring
status. Connected to the power management chip clock oscillator Y6 external
power management chip to monitor the line to provide the basis 32.768kHz clock
signal. If you do not have this clock signal, the power management chip will also
be in a "paralyzed" state. -
Power Management IC 2 feet for the start signal to detect motion foot NBSWON #.
Under normal circumstances, when the pin is detected over a negative pulse
signal, the chip that was press the power button on the boot, and immediately turn
signal through the first 4PIN of DNBSWON # "reported to the South Bridge chips."
South Bridge chip part of the line is always in working condition. Likewise, it is
also connected to a 32.768kHz external when Zhong Jingzhen Y5, its role is to
South Bridge chip modules RTC and basic detection module reference clock.
Southbridge chip power management chip receiving the boot action to issue a
pulse signal, this chip will be the first 26PIN the S USB #, the first 69PIN high of
SUSC # set to an invalid state, the power management chip, boot up action to
provide necessary conditions.
Power management chip in the receiver to the South Bridge chip SUSB #, SUSC
# control signal "Reply" In the future, it began to issue secondary power control
signal (S5-ON, SUSON , MAINON, VRON) to each computer motherboard chip
supply voltage generated.
DC / DC power supply generating circuit will have all the appropriate supply
voltage to achieve stability in their output will be issued PWRGD high effective
signal back to the power management chip, meaning that tell it, had now been
given the task of successfully completed. Next, the power management chip
control chip can be reported to the superior work. 4 Z5 c-u $ d5 @.] - G1 D
When the power management chip to the PWRGD signal received after certain
Delay period, to again PWROK signal to the corresponding delay circuit. Delay
circuits at different delay, the order issued by the appropriate power supply OK
signal. One, SB-PWROK signal to the South Bridge chip, NB-PWROK signal to
the North Bridge chip, CPU-PWROK signal to CPU. Next, the system chipset will
issue a reset signal, first issued by the South Bridge PCI RST # signal to the PCI
bus and other related equipment and the North Bridge chip. Meanwhile, the North
Bridge chip in the receiver to the South Bridge chip issued PCIRST # reset signal,
we will send CPURST # signal to the CPU.
normal electricity supply, will enter the working state. One-chip power
management system can be understood as moments in the work of the monitoring
status. Connected to the power management chip clock oscillator Y6 external
power management chip to monitor the line to provide the basis 32.768kHz clock
signal. If you do not have this clock signal, the power management chip will also
be in a "paralyzed" state. -
Power Management IC 2 feet for the start signal to detect motion foot NBSWON #.
Under normal circumstances, when the pin is detected over a negative pulse
signal, the chip that was press the power button on the boot, and immediately turn
signal through the first 4PIN of DNBSWON # "reported to the South Bridge chips."
South Bridge chip part of the line is always in working condition. Likewise, it is
also connected to a 32.768kHz external when Zhong Jingzhen Y5, its role is to
South Bridge chip modules RTC and basic detection module reference clock.
Southbridge chip power management chip receiving the boot action to issue a
pulse signal, this chip will be the first 26PIN the S USB #, the first 69PIN high of
SUSC # set to an invalid state, the power management chip, boot up action to
provide necessary conditions.
Power management chip in the receiver to the South Bridge chip SUSB #, SUSC
# control signal "Reply" In the future, it began to issue secondary power control
signal (S5-ON, SUSON , MAINON, VRON) to each computer motherboard chip
supply voltage generated.
DC / DC power supply generating circuit will have all the appropriate supply
voltage to achieve stability in their output will be issued PWRGD high effective
signal back to the power management chip, meaning that tell it, had now been
given the task of successfully completed. Next, the power management chip
control chip can be reported to the superior work. 4 Z5 c-u $ d5 @.] - G1 D
When the power management chip to the PWRGD signal received after certain
Delay period, to again PWROK signal to the corresponding delay circuit. Delay
circuits at different delay, the order issued by the appropriate power supply OK
signal. One, SB-PWROK signal to the South Bridge chip, NB-PWROK signal to
the North Bridge chip, CPU-PWROK signal to CPU. Next, the system chipset will
issue a reset signal, first issued by the South Bridge PCI RST # signal to the PCI
bus and other related equipment and the North Bridge chip. Meanwhile, the North
Bridge chip in the receiver to the South Bridge chip issued PCIRST # reset signal,
we will send CPURST # signal to the CPU.
V2000 Power on Sequance
HP V2000
When we plugged in Adapter19VIN, the power flows to have a 5VPCU, 3VPCU voltage,
it is by the PU10 (MAX1999) automatically generated, then the machine is in standby
mode.
When we press the Power Button, NBSWON # moment there is a low level, which gave
low 97551,97551 received signal to generate signals DNBSWON #, DNBSWON
distributed to South Bridge, also issued S5-ON 11th pin to 1845 produce 1.5V_S5. S5-
ON input PQ128 PQ132 generated through S5-OND.
S5-OND and PQ141 PQ127 were generated by 5V_S5 and 3V_S5.
3V_S5, 5V_S5, 1.5V_S5 time power to the South Bridge.
South Bridge received DNBSWON low, it occurs SUSB #, SUSC # 2 high sent to 97551,
97551 received SUSB #, SUSC # after have had a SUSON, MAINON #, VRON. SUSON
signals into SUSD signal sent PQ143, PQ145 tube arises 3VSUS, 5VSUS, and SUSON
sent to MAX1845 generate 2.5VSUS.
MAINON # generated by PU7 SMDDR-VTERM. At the same time and by PQ119 PQ125
into MAIND send PQ143, PQ145, PQ148, PQ153 produce +3 V, +5 V, +2.5 V, +1.5 V
voltages.
VRON gave PU9 (MAX1907), PU5 (1992E) generated VCC-CORE and VCCP voltage.
PU6, PU4 signals generated HWPG to 97,551, then PU3, PU5 also various feedback
signals to generate a HWPG 97551.
At this point the M / B of the main voltage in each group have been OK back HWPG
voltage feedback signal with convergence, the equivalent of a HWPG "and" relationship,
such as including any group for the low feedback HWPG this POWER OK 97551 occurs
when the instruction to turn off opening of voltage, such as the OK is HWPG constant as
high as 97,551, after receiving HWPG produce PWROK signal sent to SB Southbridge,
Southbridge SB produced after the PCI RST # generated through U42 PCIRST # passed to
North Bridge. North Bridge before they produce the CPURST #.
it is by the PU10 (MAX1999) automatically generated, then the machine is in standby
mode.
When we press the Power Button, NBSWON # moment there is a low level, which gave
low 97551,97551 received signal to generate signals DNBSWON #, DNBSWON
distributed to South Bridge, also issued S5-ON 11th pin to 1845 produce 1.5V_S5. S5-
ON input PQ128 PQ132 generated through S5-OND.
S5-OND and PQ141 PQ127 were generated by 5V_S5 and 3V_S5.
3V_S5, 5V_S5, 1.5V_S5 time power to the South Bridge.
South Bridge received DNBSWON low, it occurs SUSB #, SUSC # 2 high sent to 97551,
97551 received SUSB #, SUSC # after have had a SUSON, MAINON #, VRON. SUSON
signals into SUSD signal sent PQ143, PQ145 tube arises 3VSUS, 5VSUS, and SUSON
sent to MAX1845 generate 2.5VSUS.
MAINON # generated by PU7 SMDDR-VTERM. At the same time and by PQ119 PQ125
into MAIND send PQ143, PQ145, PQ148, PQ153 produce +3 V, +5 V, +2.5 V, +1.5 V
voltages.
VRON gave PU9 (MAX1907), PU5 (1992E) generated VCC-CORE and VCCP voltage.
PU6, PU4 signals generated HWPG to 97,551, then PU3, PU5 also various feedback
signals to generate a HWPG 97551.
At this point the M / B of the main voltage in each group have been OK back HWPG
voltage feedback signal with convergence, the equivalent of a HWPG "and" relationship,
such as including any group for the low feedback HWPG this POWER OK 97551 occurs
when the instruction to turn off opening of voltage, such as the OK is HWPG constant as
high as 97,551, after receiving HWPG produce PWROK signal sent to SB Southbridge,
Southbridge SB produced after the PCI RST # generated through U42 PCIRST # passed to
North Bridge. North Bridge before they produce the CPURST #.
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